JPH0214146U - - Google Patents
Info
- Publication number
- JPH0214146U JPH0214146U JP9121788U JP9121788U JPH0214146U JP H0214146 U JPH0214146 U JP H0214146U JP 9121788 U JP9121788 U JP 9121788U JP 9121788 U JP9121788 U JP 9121788U JP H0214146 U JPH0214146 U JP H0214146U
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- circuit
- debugging
- simulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
- Debugging And Monitoring (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9121788U JPH0214146U (en]) | 1988-07-09 | 1988-07-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9121788U JPH0214146U (en]) | 1988-07-09 | 1988-07-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0214146U true JPH0214146U (en]) | 1990-01-29 |
Family
ID=31315702
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9121788U Pending JPH0214146U (en]) | 1988-07-09 | 1988-07-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0214146U (en]) |
-
1988
- 1988-07-09 JP JP9121788U patent/JPH0214146U/ja active Pending